www.irf.com 1 03/03/06 IRFB4020PBF notes through are on page 2 description this digital audio mosfet is specifically designed for class-d audio amplifier applications. this mosfet utilizes the latest processing techniques to achieve low on-resistance per silicon area. furthermore, gate charge, body-diode reverse recovery and internal gate resistance are optimized to improve key class-d audio amplifier performance factors such as efficiency, thd and emi. additional features of this mosfet are 175c operating junction temperature and repetitive avalanche capability. these features combine to make this mosfet a highly efficient, robust and reliable device for classd audio amplifier applications. s d g
to-220ab features ? key parameters optimized for class-d audio amplifier applications ? low r dson for improved efficiency ? low q g and q sw for better thd and improved efficiency ? low q rr for better thd and lower emi ? 175c operating junction temperature for ruggedness ? can deliver up to 300w per channel into 8 ? load in half-bridge configuration amplifier v ds 200 v r ds(on) typ. @ 10v 80 m q g typ. 18 nc q sw typ. 6.7 nc r g(int) typ. 3.2 ? t j max 175 c key parameters absolute maximum ratings parameter units v ds drain-to-source voltage v v gs gate-to-source voltage i d @ t c = 25c continuous drain current, v gs @ 10v a i d @ t c = 100c continuous drain current, v gs @ 10v i dm pulsed drain current p d @t c = 25c power dissipation w p d @t c = 100c power dissipation linear derating factor w/c t j operating junction and c t stg storage temperature range soldering temperature, for 10 seconds (1.6mm from case) mounting torque, 6-32 or m3 screw thermal resistance parameter typ. max. units r jc junction-to-case ??? 1.43 r cs case-to-sink, flat, greased surface 0.50 ??? c/w r ja junction-to-ambient ??? 62 max. 13 52 20 200 18 100 52 0.70 10lb in (1.1n m) -55 to + 175 300
2 www.irf.com s d g repetitive rating; pulse width limited by max. junction temperature. starting t j = 25c, l = 1.62mh, r g = 25 ? , i as = 11a. pulse width 400s; duty cycle 2%. r is measured at
limited by tjmax. see figs. 14, 15, 17a, 17b for repetitive avalanche information. electrical characteristics @ t j = 25c (unless otherwise specified) parameter min. typ. max. units bv dss drain-to-source breakdown voltage 200 ??? ??? v ? v dss / ? t j breakdown voltage temp. coefficient ??? 0.23 ??? v/c r ds(on) static drain-to-source on-resistance ??? 80 100 m ? v gs(th) gate threshold voltage 3.0 ??? 4.9 v ? v gs(th) / ? t j gate threshold voltage coefficient ??? -13 ??? mv/c i dss drain-to-source leakage current ??? ??? 20 a ??? ??? 250 i gss gate-to-source forward leakage ??? ??? 100 na gate-to-source reverse leakage ??? ??? -100 g fs forward transconductance 24 ??? ??? s q g total gate charge ??? 18 29 q gs1 pre-vth gate-to-source charge ??? 4.5 ??? q gs2 post-vth gate-to-source charge ??? 1.4 ??? nc q gd gate-to-drain charge ??? 5.3 ??? q godr gate charge overdrive ??? 6.8 ??? see fig. 6 and 18 q sw switch char g e (q gs2 + q gd ) ??? 6.7 ??? r g(int) internal gate resistance ??? 3.2 ??? ? t d(on) turn-on delay time ??? 7.8 ??? t r rise time ??? 12 ??? t d(off) turn-off delay time ??? 16 ??? ns t f fall time ??? 6.3 ??? c iss input capacitance ??? 1200 ??? c oss output capacitance ??? 91 ??? pf c rss reverse transfer capacitance ??? 20 ??? c oss eff. effective output capacitance ??? 110 ??? l d internal drain inductance ??? 4.5 ??? between lead, nh 6mm (0.25in.) l s internal source inductance ??? 7.5 ??? from package avalanche characteristics parameter units e as sin g le pulse avalanche ener g y mj i ar avalanche current a e ar repetitive avalanche ener g y mj diode characteristics parameter min. typ. max. units i s @ t c = 25c continuous source current ??? ??? 18 (body diode) a i sm pulsed source current ??? ??? 52 (body diode) v sd diode forward voltage ??? ??? 1.3 v t rr reverse recovery time ??? 82 120 ns q rr reverse recovery charge ??? 280 420 nc ??? 94 see fig. 14, 15, 16a, 16b i d = 11a typ. max. ? = 1.0mhz, see fig.5 t j = 25c, i f = 11a di/dt = 100a/s t j = 25c, i s = 11a, v gs = 0v showing the integral reverse p-n junction diode. conditions v gs = 0v, i d = 250a reference to 25c, i d = 1ma v gs = 10v, i d = 11a v ds = v gs , i d = 100a v ds = 200v, v gs = 0v v gs = 0v, v ds = 0v to 160v v ds = 200v, v gs = 0v, t j = 125c v gs = 20v v gs = -20v v gs = 10v i d = 11a v gs = 0v mosfet symbol r g = 2.4 ? v ds = 50v, i d = 11a conditions and center of die contact v dd = 100v, v gs = 10v v ds = 100v v ds = 50v
www.irf.com 3 fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. normalized on-resistance vs. temperature fig 6. typical gate charge vs.gate-to-source voltage fig 5. typical capacitance vs.drain-to-source voltage 0.1 1 10 100 v ds , drain-to-source voltage (v) 0.01 0.1 1 10 100 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 15v 12v 10v 8.0v 7.0v 6.0v 5.5v bottom 5.0v 60s pulse width tj = 25c 5.0v 0.1 1 10 100 v ds , drain-to-source voltage (v) 0.1 1 10 100 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 5.0v 60s pulse width tj = 175c vgs top 15v 12v 10v 8.0v 7.0v 6.0v 5.5v bottom 5.0v -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 11a v gs = 10v 1 10 100 1000 v ds , drain-to-source voltage (v) 10 100 1000 10000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 0 5 10 15 20 q g , total gate charge (nc) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 160v v ds = 100v v ds = 40v i d = 11a 2 3 4 5 6 7 8 v gs , gate-to-source voltage (v) 0.1 1 10 100 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) t j = 25c t j = 175c v ds = 25v 60s pulse width
4 www.irf.com fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. junction temperature fig 7. typical source-drain diode forward voltage fig 8. maximum safe operating area fig 10. threshold voltage vs. temperature 0.2 0.4 0.6 0.8 1.0 1.2 v sd , source-to-drain voltage (v) 0.1 1 10 100 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 25 50 75 100 125 150 175 t j , junction temperature (c) 0 2 4 6 8 10 12 14 16 18 20 i d , d r a i n c u r r e n t ( a ) -75 -50 -25 0 25 50 75 100 125 150 175 200 t j , temperature ( c ) 1.0 2.0 3.0 4.0 5.0 v g s ( t h ) , g a t e t h r e s h o l d v o l t a g e ( v ) i d = 100a 1e-006 1e-005 0.0001 0.001 0.01 0.1 1 10 100 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc j j 1 1 2 2 3 3 r 1 r 1 r 2 r 2 r 3 r 3 ci i / ri ci= i / ri c 4 4 r 4 r 4 ri (c/w) i (sec) 0.0283 0.000007 0.3659 0.000140 0.7264 0.001376 0.3093 0.007391 1 10 100 1000 v ds , drain-to-source voltage (v) 0.001 0.01 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) operation in this area limited by r ds (on) tc = 25c tj = 175c single pulse 100sec 1msec 10msec dc
www.irf.com 5 fig 13. maximum avalanche energy vs. drain current fig 12. on-resistance vs. gate voltage fig 14. typical avalanche current vs.pulsewidth fig 15. maximum avalanche energy vs. temperature notes on repetitive avalanche curves , figures 14, 15: (for further info, see an-1005 at www.irf.com) 1. avalanche failures assumption: purely a thermal phenomenon and failure occurs at a temperature far in excess of t jmax . this is validated for every part type. 2. safe operation in avalanche is allowed as long ast jmax is not exceeded. 3. equation below based on circuit and waveforms shown in figures 17a, 17b. 4. p d (ave) = average power dissipation per single avalanche pulse. 5. bv = rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. i av = allowable avalanche current. 7. ? t = allowable rise in junction temperature, not to exceed t jmax (assumed as 25c in figure 14, 15). t av = average time in avalanche. d = duty cycle in avalanche = t av f z thjc (d, t av ) = transient thermal resistance, see figure 11) p d (ave) = 1/2 ( 1.3bvi av ) = t/ z thjc i av = 2 t/ [1.3bvz th ] e as (ar) = p d (ave) t av 5 6 7 8 9 10 11 12 13 14 15 16 v gs, gate -to -source voltage (v) 50 75 100 125 150 175 200 225 250 275 300 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( m ? ) i d = 11a t j = 25c t j = 125c 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 100 200 300 400 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 1.6a 2.4a bottom 11a 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 tav (sec) 0.01 0.1 1 10 100 1000 a v a l a n c h e c u r r e n t ( a ) 0.05 duty cycle = single pulse 0.10 allowed avalanche current vs avalanche pulsewidth, tav assuming ? tj = 25c due to avalanche losses 0.01 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 20 40 60 80 100 e a r , a v a l a n c h e e n e r g y ( m j ) top single pulse bottom 1.0% duty cycle i d = 11a
6 www.irf.com fig 16b. unclamped inductive waveforms fig 16a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v v gs fig 17a. switching time test circuit fig 17b. switching time waveforms v gs v ds 90% 10% t d(on) t d(off) t r t f v gs pulse width < 1s duty factor < 0.1% v dd v ds l d d.u.t + - fig 18a. gate charge test circuit fig 18b gate charge waveform vds vgs id vgs(th) qgs1 qgs2 qgd qgodr 1k vcc dut 0 l
www.irf.com 7 data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 03/06 to-220ab packages are not recommended for surface mount application.
note: "p" in assembly line position indicates "lead-free"
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